Verilog TestBench Design

I have be working on my side project of digital circuit design in Verilog for a while. One thing that bugs me and pops up regularly is the way to write a test. I have a few options here:

1. I can go for the old school style to embedded the test as blocks of Verilog code in the testbench. This give me the largest flexibility in terms of precise control of the testing environment. But this is also the most troublesome style. It requires the test author to code in Verilog. It exposes the complexity and diversity of the DUT to the test author. It is difficult to build and hard to debug. It also require re-compilation for even the simplest change in the test.
2. Most comercial Verilog simulator supports a build scripting engine which allows an interactive user experience through the simulator consoles. These include VCS, Incisive and ModelSim. TCL is the most commonly supported scripting language in these EDA tools. So one can build the complete test environment around this technology. The largest advantage is the easy of coding in a familiar syntax while maintaining fine control over the DUT through the TCL commands provided by the EDA tool. No recompilation is required. I have seen this approach in practical environment for IP design. It works very well, as long as you have paid for the simulator. Unfortunately, I cannot find any free Verilog simulator supporting this, not to said that I have to run it on my Macbook Air.
3. UVM+SV is the trendy thingy in SoC/IP design. I sure you that there are tons of information you can get from Google telling its advantages. But again, I cannot find a free (either as beer or for speech) Verilog simulator supporting this.
4. The approach I used is adapted from the company I worked for. The implementation is completely different by the underlying idea is the same. To write a standard test vector generator which will read in a text based test file. It then alters the signals connected to the DUT based on parsing the text file line by line. A simple programming language with a handful of instructions and a text editor are all you need to create and modify a test. This works fine until you try more complicate tests with branch and arithmetic operations

Now I am working on another approach which:

• doest not require recompilation of the Verilog code (this is very important as we cannot assume the person who creates and runs the test will have access to the same Verilog compiler, also, you can ship binary instead of source code to the testing environment)
• has a simple programming interface. It may not be as flexible and mature as TCL, but it should support simple looping and arithmetic operations.
• is independent from the Verilog compiler and simulator. This will ensure the portability of the tests and allow future extension.